1. Field of the Invention
The present invention generally relates to a semiconductor device and, more particularly, to an improved semiconductor device having a well which is isolated from a substrate and is of the same conductivity type as that of the substrate so that the well and the substrate may not interfere with each other, even when a large amount of minority carriers are implanted. The present invention further relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
FIG. 8 is a cross-sectional view of a conventional semiconductor device including a well of two-layered structure. A P type semiconductor substrate 1 has, provided at a main surface, N wells 5, 6, and a P well 2 and a P well 3 provided adjacent thereto. In addition, a P well 4 is provided in the N well 6.
A dynamic random access memory as shown in FIG. 9 is, for example, formed in the P well 4. Referring to FIGS. 8 and 9, the N well 6 is provided in the P type semiconductor substrate 1 and the P well 4 is provided in the N well 6. A word line 32 is provided at the main surface of the P well 4. N.sup.+ diffusion layers 21 (each hereinafter referred to as an N.sup.+ layer) are provided at the main surface of the P well 4 at both sides of the word line 32. A storage node 33 is connected to one of the N.sup.+ layers 21, and a cell plate 34 is provided on the storage node 33 with a capacitor insulating film 36 interposed therebetween. A bit line 31 is connected to the other of the N.sup.+ layers 21.
Advantages of the well of two-layered structure shown in FIG. 8 will now be described.
Referring to FIG. 8, the P well 4 is isolated by junctions from the P wells 2, 3 directly formed at the main surface of the P type semiconductor substrate 1 with the N wells 5, 6 interposed therebetween. As a result, since the P well 4 seldom interferes with the P wells 2, 3, devices (not shown) formed in respective wells and affecting each other can be isolated from each other. A device element likely to be affected by implantation of minority carriers can also be isolated from other device elements. For example, even if minority carriers are generated in the P well 4, these minority carriers are absorbed in the N well 6, whereby they do not reach device elements (not shown) formed in the P wells 2, 3 which are likely to be affected by implantation of minority carriers.
While the well of two-layered structure has advantages as described above, it also has disadvantages described in the following.
Referring to FIG. 10, when a large amount of minority carriers are implanted in the P well 4 at a time, the N well 6 absorbs the minority carriers a lot, whereby an increase in resistance component is caused in the N well 6, which results in a voltage drop. As a result, when a region 6a in the N well 6 directly beneath the N.sup.+ layer. 21 becomes a low potential, the region 6a becomes forward biased with respect to the P type semiconductor substrate 1. As a result, a PNP transistor is turned on and interference occurs between the P well 4 and the P type semiconductor substrate 1.
Referring to FIG. 11, when a voltage of 4.3 V exceeding 3.3 V is applied to the P.sup.+ layer 22 provided in the main surface of the N well 5, a large amount of minority carriers are implanted in the N well 5 from the P.sup.+ layer 22. In this case, high potential portions are produced by implantation of high potential carriers in P type regions 4a, 3a, 1a of the P well 4, the P well 3 and the P type semiconductor substrate 1 which are adjacent the N well 5. This causes, for example, the P well 4 and the N.sup.+ layer 21 to be biased in a forward direction, whereby a current flows in the N.sup.+ layer 21 and erases storage information of, for example, a DRAM.
As described above, a conventional well having two-layered structure was likely to be affected by implantation of a large amount of minority carriers. Referring to FIG. 10, there were various problems to be solved that it was necessary to increase a concentration of the N well 6 at the sacrifice of a junction breakdown so as not to generate a voltage drop, or to divide the N well 6 into smaller wells at the sacrifice of degree of integration.